1. Field of the Invention
The present invention relates to an apparatus and a method for polishing semiconductor device. More specifically it relates to an improvement in apparatus and method for polishing semiconductor device with respect to the hardness of the polish and back pads.
2. Description of the Related Art
In the manufacture of semiconductor devices it is normal for irregularities or unevenness to occur on the surface of the semiconductor wafer or substrate as a result, for example, patterning of MOS transistor active components or aluminum wiring. In other words, surface irregularities in the component area or along the aluminum wiring appear also as irregularities on the surface of the interlayer dielectric film which is formed on the semiconductor wafer. These surface irregularities affect the accuracy of processing dimensions during the later process of forming the upper-layer wiring, particularly in the lithography process.
Recent years have witnessed a reduction in wiring pitch and advances in multilayer wiring, as a result of which it has become vital to ensure that the surface of the semiconductor wafer is flat. Consequently, it has become impossible to satisfy the requirements for planarization in the process of manufacturing semiconductors by employing conventional methods of filling concave sections of the interlayer dielectric in with spin-on glass and similar flow coatings.
The principal method in use at present is known as chemical and mechanical polishing (CMP). FIG. 6 shows how a semiconductor wafer is polished using a conventional polishing apparatus. A soft material 51 and a hard material 52 are made to adhere in laminated fashion to the upper surface of a revolving platen 50, the soft material 51 acting as a soft pad and the hard material 52 as a hard pad, while together they constitute a polish pad. When a semiconductor wafer 53 is to be polished, an abrasive agent 54 is fed on to the abovementioned polish pad. The semiconductor wafer is fixed to the under surface of a spindle 55, its surface being polished by rotating the platen 50 and the spindle 55 in the same direction while applying a prescribed pressure in order to press on to the polish pad the exposed surface which is to be polished. This method is widely used for polishing interlayer dielectrics, component-separating films, metal films and other items.
FIG. 7 is a drawing which illustrates the conventional method for polishing a semiconductor wafer. It will be used to explain why the polish pad is composed of a double layer of soft material 51 and hard material 52. In this drawing, the dielectric film 56 of the semiconductor wafer 53 is shown pressed on to the polish pad consisting of the soft material 51 and hard material 52. In the drawing, 57 represents the wiring pattern which is covered by the dielectric film 56.
The application of various dielectric films 56 and metal films 57 to the semiconductor wafer 53 during the process of its manufacture means that when it comes to polishing, as the drawing shows, there is a degree of bowing which amounts to several tens of micrometers. Accordingly, surface distortion of the polish pad must be inhibited if selective polishing of convex sections of the dielectric films 56 and metal films 57 is to be attained. This is why a high degree of hardness is required. On the other hand, if the whole surface of the semiconductor wafer is to be polished uniformly, the polish pad must possess a degree of softness sufficient to offset the bowing. For this reason, and in order to achieve the twin aims of flatness and uniformity, the polish pad consists of a hard material (hard pad) 52 underlaid with a soft material (soft pad) 51.
Japanese Laid-Open Patent Application No. Hei7-297195 provides a specific example of conventional technology in relation to the polishing of semiconductor device. A double layer of polishing cloth comprising polyurethane unwoven cloth and hard foamed polyurethane is attached to a press platen. A tool covered in diamonds is applied to the under surface of the polishing cloth in order to raise the nap and shape the whole of the surface.
The technique described in the abovementioned patent normally employs Rodel-Nitta SUBA 400 (JIS spring A hardness 55-65, Shore spring A hardness 57.5-69) or Rodel SUBA IV (JIS spring A hardness 54-68, Shore spring A hardness 57-71) as the soft material which constitutes the lower layer of the polish pad (soft pad) 51. Meanwhile, Rodel IC 1000 (JIS spring A hardness 95, Shore spring A hardness 98) is employed as the hard material which constitutes the upper layer of the polish pad (hard pad) 52.
Here, JIS spring A hardness refers to the hardness as measured by means of a JIS spring type A according to the criteria described in Japanese Industrial Standards (JIS) K 6301. Shore spring A hardness signifies hardness as measured by means of a Shore spring type A. For the purpose of reference, FIG. 10 correlates the two.
However, the polish pad described in the abovementioned patent suffers from the drawback that when used to polish the semiconductor wafer 53, the rate of polishing falls in the vicinity of the center of the semiconductor wafer 53, and falls markedly in an area within a certain distance (e.g. 6 mm) of its outermost periphery. This occurs as a result of the low degree of hardness of the soft material 51 which forms the lower layer of the pad.
FIG. 8 shows how the polish pad becomes distorted as a result of the load imposed on it by the semiconductor wafer 53 in a conventional example. During polishing, as will be seen, the semiconductor wafer 53 is held by a guide ring 58. A base plate 59 is employed in order to apply a load, and the shape of the semiconductor wafer 53 is controlled by means of a back pad 60 while it is pressed against the polish pad comprising the hard material 52 and the soft material 51.
In the abovementioned method for polishing, the hard quality of the hard material 52 which forms the upper layer of the polish pad means that if its surface is distorted in a downward direction, the shape of that surface is incapable of following the curvature at the edges of the semiconductor wafer 53, as the drawing shows. The result is that the maximum load is exerted on these edges, so that localised distortion occurs in their vicinity. Consequently, not only is contact pressure reduced markedly in an area within a specified distance (e.g. 2-3 mm) of the edges, but contact pressure between the central part of the semiconductor wafer 53 and the polish pad is also reduced. This phenomenon occurs because an unnecessarily soft material is selected for use in the soft pad 51 which forms the lower layer of the polish pad, and makes it difficult to create semiconductor components within a specified distance (e.g. 6 mm) of the outermost periphery of the semiconductor wafer.
Recently, the method for polishing illustrated in FIG. 9 has been attempted with a view to solving the problems inherent in the abovementioned method. This improved method for polishing involves pressing against a polish pad comprising a soft material 51 and a hard material 52 a guide ring 81, the purpose of which is to hold the semiconductor wafer 53 during polishing. By allowing the area where the polish pad is subject to localised distortion to escape to the area outside the guide ring 81 (i.e., towards the periphery of the semiconductor wafer 53) it is possible to inhibit variation in the polishing rate in the vicinity of the outermost periphery of the semiconductor wafer 53.
However, the abovementioned improved conventional method for polishing requires the pressure with which the guide ring 81 is pressed against the polish pad to be at least equal to the polishing load which is exerted on the semiconductor wafer 53. This gives rise to unstable behaviour caused by attrition of the guide ring 81, disruption of the supply of the abrasive agent on to the polish pad by the guide ring 81, and variations in the optimal pressure on it as a result of changes in the polish pad with time. A further disadvantage accrues from the necessity for outlay in order to improve the polishing apparatus.